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ltm9003 9003f typical a pplica t ion descrip t ion 12-bit digital pre-distortion module receiver subsystem the ltm ? 9003 is a 12-bit digital pre-distortion module ? receiver subsystem for the transmit path of cellular bases- tations. utilizing an integrated system in a package (sip) technology, it includes a downconverting mixer, wideband flter and analog-to-digital converter (adc). the system is tuned for an intermediate frequency (if) of 184mhz and a signal bandwidth of up to 125mhz. the 12-bit adc samples at rates up to 250msps. contact linear technol- ogy regarding customization. the high signal level downconverting active mixer is opti- mized for high linearity, wide dynamic range if sampling applications. it includes a differential lo buffer amplifer driving a double-balanced mixer. broadband, integrated transformers on the rf and lo inputs provide single ended 50 interfaces. the rf and lo inputs are internally matched to 50 from 1.1ghz to 1.8ghz. the clk input controls converter operation and may be driven differentially or single-ended. an optional clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles. l , lt, ltc, ltm, linear technology, the linear logo and module are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents including 5481178, 6580258, 6304066, 6127815, 6498466, 6611131. fft of 4-channel wcdma input at 2.14ghz fea t ures a pplica t ions n fully integrated receiver subsystem for digital pre-distortion applications n down-converting mixer with wide rf frequency range: 400mhz to 3.8ghz n 125mhz wide bandpass filter, <0.5db passband ripple n low power adc with up to 12-bit resolution, 250msps sample rate n C145.5dbm/hz input noise floor, 25.6dbm iip3 n 1.5w total power consumption n 50 single-ended rf and lo ports n internal bypass capacitance, no external components n adc clock duty cycle stabilizer n 11.25mm 15mm lga package n transmit observation path receivers n digital pre-distortion (dpd) receivers n wideband receiver n wideband instrumentation if frequency (mhz) 154 ?110 ?90 ?100 ?80 ?50 ?60 ?70 amplitude (db) 164 174 194184 204 214 9003 ta01b ?40 ltm9003 ov dd = 2.5v dgnd enc ? enc + gnd lo 3.3v 2.5v rf 9003 ta01 pa d11 ? ? ? d0 lvds
ltm9003 9003f p in c on f igura t ion a bsolu t e maxi m u m r a t ings supply voltage (v cc1 ) ltm9003-aa ........................................... C0.3v to 4v ltm9003-ab ........................................ C0.3v to 5.5v supply voltage (v cc2 ) ................................ C03v to 5.5v supply voltage (v dd , ov dd ) ..................... C0.3v to 2.8v digital output ground voltage (ognd) ........ C0.3v to 1v lo input power (380mhz to 4.2ghz) ...................10dbm lo input dc voltage...........................C1v to (v cc1 + 1v) rf input power (400mhz to 3.8ghz) ...................15dbm rf input dc voltage ............................................... 0.1v mix_en voltage .......................... C0.3v to (v cc1 + 0.3v) amp_en input current ......................................... 10ma digital input voltage..................... C0.3v to (v dd + 0.3v) digital output voltage ................ C0.3v to (ov dd + 0.3v) operating ambient temperature range ltm9003cv ............................................. 0c to 70c ltm9003iv ..........................................C40c to 85c storage temperature range .................. C40c to 125c maximum junction temperature .......................... 125c caution: the rf and lo inputs are sensitive to electro- static discharge (esd). it is very important that proper esd precautions be observed when handling the ltm9003. (notes 1, 2) v cc2 2 3 4 5 6 7 8 9 10 11 1 12 a b c d e f g h j lga package 108-lead (15mm s 11.25mm s 2.32mm) top view v cc1 all others = gnd data, control amp_en enc ? enc + v dd ov dd rf lo mix_en t jmax = 125c, q ja = 16.5c/w, q jctop = 15c/w, q jcbot = 6.3c/w, q jb = 10.4c/w derived from 101.5mm s 114.5mm pcb with 4 layers weight = 0.95g o r d er i n f or m a t ion lead free finish tray part marking* package description temperature range ltm9003cv-aa#pbf ltm9003cv-aa#pbf ltm9003v aa 108-lead (11.25mm s 15mm s 2.3mm) lga 0c to 70c ltm9003iv-aa#pbf ltm9003iv-aa#pbf ltm9003v aa 108-lead (11.25mm s 15mm s 2.3mm) lga C40c to 85c ltm9003cv-ab#pbf ltm9003cv-ab#pbf ltm9003v ab 108-lead (11.25mm s 15mm s 2.3mm) lga 0c to 70c ltm9003iv-ab#pbf ltm9003iv-ab#pbf ltm9003v ab 108-lead (11.25mm s 15mm s 2.3mm) lga C40c to 85c consult ltc marketing for parts specifed with wider operating temperature ranges. *the temperature grade is identifed by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ this product is only offered in trays. for more information go to: http://www.linear.com/packaging/
ltm9003 9003f e lec t rical c harac t eris t ics the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. (note 3) parameter conditions min typ max units rf input frequency range ltm9003-aa no external matching (midband) with external matching (low band or high band) 400 1100 to 1800 3800 mhz mhz ltm9003-ab no external matching (midband) with external matching (low band or high band) 400 1100 to 1800 3700 mhz mhz lo input frequency range ltm9003-aa no external matching with external matching 380 800 to 3500 mhz mhz ltm9003-ab no external matching with external matching 380 900 to 3500 mhz mhz rf input return loss z o = 50, 1100mhz to 1800mhz (no external matching) ltm9003-aa ltm9003-ab >12 >12 db db lo input return loss z o = 50, 900mhz to 3500mhz (no external matching) ltm9003-aa ltm9003-ab >10 >10 db db rf input power for C1dbfs ltm9003-aa ltm9003-ab C1.7 C1.7 dbm dbm lo input power 1200mhz to 4200mhz, ltm9003-aa or 1200mhz to 3500mhz, ltm9003-ab 380mhz to 1200mhz C8 C5 C3 0 2 5 dbm dbm lo to rf leakage ltm9003-aa f lo = 380mhz to 1600mhz f lo = 1600mhz to 4000mhz 50 >42 db db ltm9003-ab f rf = 400mhz to 2200mhz f rf = 2200mhz to 3700mhz >43 >38 db db c onver t er c harac t eris t ics the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. (note 3) parameter conditions min typ max units resolution (no missing codes) l 12 bits integral linearity error (note 4) if = 184.32mhz 1 lsb differential linearity error if = 184.32mhz 0.4 lsb
ltm9003 9003f dyna m ic a ccuracy symbol parameter conditions min typ max units snr signal-to-noise ratio at C1dbfs rf = 1889mhz, lo = 1766mhz rf = 1950mhz, lo = 1766mhz rf = 2011mhz, lo = 1766mhz l 141 143.6 143.6 143.6 db/hz db/hz db/hz iip3 input 3rd order intercept, 2-tone ltm9003-aa rf = 1948mhz, 1952mhz, lo = 1766mhz 27 dbm ltm9003-ab rf = 1948mhz, 1952mhz, lo = 1766mhz 28 dbm iip2 input 2nd order intercept, 1-tone ltm9003-aa rf = 1950mhz, lo = 1766mhz 61 dbm ltm9003-ab rf = 1950mhz, lo = 1766mhz 61.4 dbm sfdr spurious free dynamic range, 2nd or 3rd harmonic at C1dbfs ltm9003-aa rf = 1889mhz, lo = 1766mhz rf = 1950mhz, lo = 1766mhz rf = 2011mhz, lo = 1766mhz l 50.7 54.1 58.8 63.6 db db db ltm9003-ab rf = 1889mhz, lo = 1766mhz rf = 1950mhz, lo = 1766mhz rf = 2011mhz, lo = 1766mhz l 52.0 57.3 62.4 66.3 db db db sfdr spurious free dynamic range, 4th or higher at C1dbfs rf = 1889mhz, lo = 1766mhz rf = 1950mhz, lo = 1766mhz rf = 2011mhz, lo = 1766mhz l 66.5 74 82 87 db db db s/(n+d) signal-to-noise plus distortion ratio at C1dbfs rf = 1889mhz, lo = 1766mhz rf = 1950mhz, lo = 1766mhz rf = 2011mhz, lo = 1766mhz l 50.3 54 58 60 db db db imd3 intermodulation distortion at C7dbfs per tone rf = 1950mhz, lo = 1766mhz C58 db acpr adjacent channel power ratio at 2.4dbm per carrier, four carriers 58.5 db altcpr alternate channel power ratio at 2.4dbm per carrier, four carriers 63.3 db the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. (note 3) fil t er c harac t eris t ics the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. parameter conditions min typ max units center frequency 184.32 mhz lower 3db bandedge 84 mhz upper 3db bandedge 304 mhz lower 20db stopband 40 mhz upper 20db stopband 450 mhz passband flatness 129mhz to 239.6mhz 174mhz to 194mhz 0.5 0.15 db db group delay flatness 129mhz to 239.6mhz 174mhz to 194mhz 1.2 0.1 ns ns absolute delay 2.7 ns
ltm9003 9003f symbol parameter conditions min typ max units encode inputs (enc C , enc + ) v id differential input voltage (note 5) 0.2 v v icm common mode input voltage internally set externally set (note 5) l 1.2 1.5 1.5 2 v v r in input resistance single-ended 4.8 r in(diff) input resistance differential 100 c in input capacitance 2 pf logic inputs (oe, shdn) v ih high level input voltage v dd = 2.5v l 1.7 v v il low level input voltage v dd = 2.5v l 0.7 v i in input current v in = 0v to v dd l C10 10 a c in input capacitance (note 5) 3 pf mixer enable v ih high level input voltage v cc1 = 3.3v, ltm9003-aa v cc1 = 5v, ltm9003-ab l l 2.7 3 v v v il low level input voltage v cc1 = 3.3v, ltm9003-aa v cc1 = 5v, ltm9003-ab l l 0.3 0.3 v v i in input current v in = 0v to v cc1 , ltm9003-aa l 53 90 a turn-on time 2.8 ms turn-off time 2.9 ms amplifer enable v ih high level input voltage v cc2 = 3.3v l 2 v v il low level input voltage v cc2 = 3.3v l 0.8 v i in input current v in = 0.8v v in = 2v l l C200 C150 C85 C30 0 0 a a control inputs (sense, mode, lvds) i sense sense input leakage 0v < sense < 1v l C1 1 a i mode mode pull-down current to gnd see pin functions for voltage levels 7 a i lvds lvds pull-down current to gnd see pin functions for voltage levels 7 a logic outputs (lvds mode) ov dd = 2.5v v od differential output voltage 100 differential load l 247 350 454 mv v os output common mode voltage 100 differential load l 1.125 1.250 1.375 v digi t al i npu t s an d o u t pu t s the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. (note 3)
ltm9003 9003f p ower r equire m en t s symbol parameter conditions min typ max units v cc1 mixer supply range ltm9003-aa (note 6) ltm9003-ab (note 6) l l 2.9 4.5 3.3 5 3.6 5.25 v v v cc2 amplifer supply range (note 6) l 2.8 3.3 5.25 v v dd adc analog supply voltage (note 6) l 2.375 2.5 2.625 v i cc1 mixer supply current mix_en = 3v, ltm9003-aa mix_en = 5v, ltm9003-ab l 80 82 92 92 ma ma i cc1(shdn) mixer shutdown supply current mix_en = 0v l 100 a i cc2 amplifer supply current amp_en = 3v l 104 140 ma i cc2(shdn) amplifer shutdown supply current amp_en = 0v l 3 5 ma i dd(adc) adc supply current l 285 320 ma p d(shdn) adc shutdown power shdn = v dd , oe = v dd , no clk 1.5 mw p d(nap) adc nap mode power shdn = v dd , oe = 0v, no clk 30 mw lvds output mode ov dd adc digital output supply voltage l 2.375 2.5 2.625 v i ovdd(adc) adc digital output supply current l 58 74 ma p d(adc) adc power dissipation l 858 985 mw p d(total) total power dissipation shdn = 0v, mix_en = amp_en = 3v, f sample = max (ltm9003-aa) (ltm9003-ab) 1465 1611 mw mw the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. (note 3)
ltm9003 9003f ti m ing c harac t eris t ics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all voltage values are with respect to ground with gnd and ognd wired together (unless otherwise noted). symbol parameter conditions min typ max units f s sampling frequency (note 6) l 1 250 mhz t l enc low time duty cycle stabilizer off (note 5) duty cycle stabilizer on (note 5) l l 1.9 1.5 2 2 500 500 ns ns t h enc high time duty cycle stabilizer off (note 5) duty cycle stabilizer on (note 5) l l 1.9 1.5 2 2 500 500 ns ns t jitter sample-and-hold acquisition delay time jitter 95 fs rms t ap sample-and-hold aperture delay 0 ns t oe output enable delay (note 5) l 5 10 ns lvds output mode t d enc to data delay (note 5) l 1 1.7 2.8 ns t c enc to clkout delay (note 5) l 1 1.7 2.8 ns data to clkout skew (t c C t d ) (note 5) l C0.6 0 0.6 ns rise time 0.5 ns fall time 0.5 ns pipeline latency 5 cycles the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. (note 3) note 3: v cc1 = v cc2 = 3.3v (ltm9003-aa) or v cc1 = 5v, v cc2 = 3.3v (ltm9003 - ab), v dd = 2.5v, ov dd = 2.5v, f sample = 250mhz, input range = C1dbfs, differential enc + /enc C = 2v pCp sine wave, unless otherwise noted. note 4: integral nonlinearity is defned as the deviation of a code from a best straight line ft to the transfer curve. the deviation is measured from the center of the quantization band. note 5: guaranteed by design, not subject to test. note 6: recommended operating conditions.
ltm9003 9003f ti m ing diagra m lvds output mode timing all outputs are differential and have lvds levels t h t d t c t l n ? 5 n ? 4 n ? 3 n ? 2 n ? 1 t ap n + 1 n + 2 n + 4 n + 3 n analog input enc ? enc + clkout ? clkout + d0-d11, of 9003 td01
ltm9003 9003f typical p er f or m ance c harac t eris t ics if frequency response, ltm9003-aa if frequency response, ltm9003-aa 64k point fft, ltm9003-aa 64k point 2-tone fft, ltm9003-aa snr vs frequency, ltm9003-aa frequency (mhz) 0 amplitude (dbfs) 0 ?20 ?40 ?60 ?80 ?100 ?10 ?30 ?50 ?70 ?90 ?110 ?120 40 80 20 60 100 9003 g01 120 f in = 1950mhz ?1dbfs sense = v dd frequency (mhz) 0 amplitude (dbfs) 0 ?20 ?40 ?60 ?80 ?100 ?10 ?30 ?50 ?70 ?90 ?110 ?120 40 80 20 60 100 9003 g02 120 f in = 1948mhz, f in = 1952mhz ?7dbfs per tone sense = v dd if frequency (mhz) 10 snr (dbfs) 66 64 62 65 63 61 60 210 310 16011060 260 360 9003 g03 410 f in = 2.14ghz if frequency (mhz) amplitude (dbfs) 0 ?1.0 ?2.0 ?0.5 ?1.5 ?2.5 ?3.0 210 160135110 235 185 9003 g04 260 f in = 2.14ghz if frequency (mhz) 10 amplitude (dbfs) 210 310 16011060 260 360 9003 g05 410 0 ?20 ?40 ?10 ?5 ?30 ?25 ?15 ?35 ?45 ?50 f in = 2.14ghz t a = 25c.
ltm9003 0 9003f typical p er f or m ance c harac t eris t ics 64k point fft, ltm9003-ab 64k point 2-tone fft, ltm9003-ab snr vs frequency, ltm9003-ab frequency (mhz) 0 amplitude (dbfs) 0 ?20 ?40 ?60 ?80 ?100 ?10 ?30 ?50 ?70 ?90 ?110 ?120 40 80 20 60 100 9003 g06 120 f in = 1950mhz ?1dbfs sense = v dd frequency (mhz) 0 amplitude (dbfs) 0 ?20 ?40 ?60 ?80 ?100 ?10 ?30 ?50 ?70 ?90 ?110 ?120 40 80 20 60 100 9003 g07 120 f in = 1948mhz, f in = 1952mhz ?7dbfs per tone sense = v dd if frequency (mhz) 10 snr (dbfs) 66 64 62 65 63 61 60 210 310 16011060 260 360 9003 g08 410 f in = 2.14ghz if frequency response, ltm9003-ab if frequency response, ltm9003-ab if frequency (mhz) amplitude (db) 0 ?1.0 ?2.0 ?0.5 ?1.5 ?2.5 ?3.0 210 160135110 235 185 9003 g09 260 f in = 2.14ghz if frequency (mhz) 10 amplitude (dbfs) 210 310 16011060 260 360 9003 g10 410 0 ?20 ?40 ?10 ?5 ?30 ?25 ?15 ?35 ?45 ?50 f in = 2.14ghz t a = 25c.
ltm9003 9003f p in func t ions v cc1 (pins e1, e2, f2): 3.3v (ltm9003-aa) or 5v (ltm9003-ab) supply voltage for the mixer. v cc1 is internally bypassed to gnd. v cc2 (pins b1, b2): 3.3v supply voltage for the amplifer. v cc2 is internally bypassed to gnd. v dd (pins d11, e7, e8): 2.5v supply voltage for adc. v dd is internally bypassed to gnd. ov dd (pins g12, h9, h11): 2.5v supply for the output drivers. ov dd is internally bypassed to ognd. gnd (see table for locations): module ground. ognd (pins f12, h8, h10, h12, j12): output driver ground. rf (pin g1): single-ended input for the rf signal. this pin is internally connected to the primary side of the rf input transformer, which has low dc resistance to ground. if the rf source is not dc blocked, then a series blocking capacitor must be used. the rf input is internally matched from 1.1ghz to 1.8ghz. operation down to 400mhz or up to 3.8ghz is possible with simple external matching. lo (pin j2): single-ended input for the local oscillator signal. this pin is internally connected to the primary side of the lo transformer, which is internally dc blocked. an external blocking capacitor is not required. the lo input is internally matched from 0.9ghz to 3.5ghz. operation down to 380mhz is possible with simple external matching. mix_en (pin f4): mixer enable pin. connecting mix_en to v cc1 results in normal operation. connecting mix_en to gnd disables the mixer. the mix_en pin should not be left foating. amp_en (pin c3): amplifer enable pin. this pin is internally pulled high by a typically 30k resistor to v cc2 . connecting amp_en to v cc2 results in normal operation. connecting amp_en to gnd disables the amplifer. enc + (pin d12): adc encode input. conversion starts on the positive edge. enc C (pin e12): adc encode complement input. conver- sion starts on the negative edge. bypass to ground with 0.1f ceramic for single-ended encode signal. shdn (pin b11): adc shutdown mode selection pin. con- necting shdn to gnd and oe to gnd results in normal operation with the outputs enabled. connecting shdn to gnd and oe to v dd results in normal operation with the outputs at high impedance. connecting shdn to v dd and oe to gnd results in nap mode with the outputs at high impedance. connecting shdn to v dd and oe to v dd results in sleep mode with the outputs at high impedance. oe (pin c11): output enable pin. refer to shdn pin function. mode (pin c7): output format and clock duty cycle stabilizer selection pin. connecting mode to gnd selects offset binary output format and turns the clock duty cycle stabilizer off. 1/3 v dd selects offset binary output format and turns the clock duty cycle stabilizer on. 2/3 v dd selects 2s complement output format and turns the clock duty cycle stabilizer on. v dd selects 2s complement output format and turns the clock duty cycle stabilizer off. sense (pin g7): reference programming pin. connecting sense to 1.25v selects the internal reference and a 0.5v input range. v dd selects the internal reference and a 1v input range. an external reference greater than 0.5v and less than 1v applied to sense selects an input range of v sense . 1v is the largest valid input range. lvds (pin d7): output mode selection pin. connect lvds to v dd . digital outputs d0 C /d0 + C d11 C /d11 + (see table for locations): lvds digital outputs. all lvds outputs require differential 100 termination resistors at the lvds receiver. d11 C /d11 + is the msb. clkout C /clkout + (pins j10/j11): lvds data valid output. latch data on rising edge of clkout C , falling edge of clkout + . of C /of + (pins e5/f5): lvds over/under flow output. high when an over or under fow has occurred.
ltm9003 9003f b lock diagra m v cc2 v dd ov dd d11 ? d0 of enc ? gnd sense lo v cc1 lpf bpf 9003 bd01 amp_en output drivers differential input low jitter clock driver 100 internal clock signals pipelined adc sections shift register/ error correction 1.25v reference range select input s/h reference buffer differential reference amplifier refh refl oe control logic mode lvds shdn enc + clkout ognd mix_en rf p in func t ions pin confguration j gnd lo gnd gnd gnd d9+ d8C d6+ d6C clkout+ clkoutC ognd h gnd gnd gnd gnd gnd d9C d8+ ognd ov dd ognd ov dd ognd g rf gnd gnd gnd gnd d10C sense d7+ d7C d5+ d5C ov dd f gnd v cc1 gnd mix_en ofp d10+ gnd gnd gnd gnd gnd ognd e v cc1 v cc1 gnd gnd ofn d11C v dd v dd gnd gnd gnd enc C d gnd gnd gnd gnd gnd d11+ lvds d4+ d3+ d1+ v dd enc + c gnd gnd amp_en gnd gnd gnd mode d4C d3C d1C oe gnd b v cc2 v cc2 gnd gnd gnd gnd gnd gnd d2+ d0+ shdn gnd a gnd gnd gnd gnd gnd gnd gnd gnd d2C d0C gnd gnd 1 2 3 4 5 6 7 8 9 10 11 12 top view of lga package (looking through component) figure 1. simplifed block diagram
ltm9003 9003f description the ltm9003 is an integrated system in a package (sip) that includes a high-speed 12-bit a/d converter, a wideband flter and an active mixer. the ltm9003 is designed for if sampling, digital pre-distortion (dpd) applications, also known as transmit observation path receivers, with rf input frequencies up to 3.8ghz. typical applications include multi- carrier base stations and telecom test instrumentation. digital pre-distortion is a technique often used in third- generation (3g) wireless base stations to improve the linearity of power amplifers (pa). improved pa linearity allows for a lower power pa to be used and therefore save a signifcant amount of power in the base station. the dpd receiver captures the pa output, digitizes it and feeds it back where the distortion can be analyzed. a complementary distortion is then introduced to the transmit dac thereby pre-distorting the signal. a signifcant factor in pa linearity is the distortion caused by the odd order intermodulation (im) products. the band- width to be digitized is equivalent to the signal bandwidth multiplied by the order of the im product to be canceled. for example, four carrier wcdma consumes 20mhz of signal bandwidth; therefore, to capture the ffth order im product requires 100mhz. the nyquist theory requires that the adc sample rate be at least twice that frequency. however, simply doubling the captured bandwidth to set the sample rate may not be the best choice. selecting the exact adc sample rate and intermediate frequency (if) depends on other factors within the system. to simplify fltering, the sample rate is often set at a multiple of the chip rate. the chip rate for wcdma is 3.84mhz; select- ing an adc sample rate of 64 times the chip rate gives 245.76msps. placing the if at 3/4ths the sample rate (f s ) gives 184.32mhz and allows the entire bandwidth to fall within the second nyquist zone. many other frequency plans may be acceptable. the following sections describe in further detail the opera- tion of each functional element of the ltm9003. the sip technology allows the ltm9003 to be customized and this is described in the semi-custom options section. the outline of the remaining sections follows the basic functional elements as shown in figure 2. figure 2. basic functional elements adc mixer filter filter if amplifier 9003 f02 the mixer dominates the noise fgure calculation as would be expected. the overall gain is optimized for the dynamic range of the adc relative to the rf input level allowed by the mixer. the equivalent cascaded noise fgure is 9.1db (ltm9003-aa) and 9.9db (ltm9003-ab). the bandpass flter is a second order l-c flter following the mixer and a lowpass flter following the amplifer provides anti-alias and noise limiting. semi-custom options the module construction affords a new level of fexibility in application-specifc standard products. standard adc and amplifer components can be integrated regardless of their process technology and matched with passive components to a particular application. the ltm9003 -aa, as the frst example, is confgured with a 12-bit adc sampling at rates up to 250msps. the total system gain is approximately 10.8db. the if is fxed by the bandpass flter at 184mhz with 125mhz bandwidth. the rf range is matched for 1.1ghz to 1.8ghz with low side lo. however, other options are possible through linear technologys semi-custom development program. linear technology has in place a program to deliver other speed, resolution, if range, gain and flter confgurations for nearly any specifed application. these semi-custom designs are based on existing adcs and amplifers with an appropriately modifed matching network. the fnal subsystem is then tested to the exact parameters defned for the application. the fnal result is a fully integrated, accurately tested and optimized solution in the same package. for more details on the semi-custom receiver subsystem program, contact linear technology. down-converting mixer the mixer stage consists of a high linearity double-bal- anced mixer, rf buffer amplifer, high speed limiting lo buffer amplifer and bias/enable circuits. the rf and lo o pera t ion
ltm9003 9003f inputs are both single ended. low side or high side lo injection can be used. the mixers rf input consists of an integrated transformer and a high linearity differential amplifer. the primary terminals of the transformer are connected to the rf input (pin g1) and ground. the secondary side of the transformer is internally connected to the amplifers dif- ferential inputs. the mixers lo input consists of an integrated transformer and high speed limiting differential amplifers. the ampli- fers are designed to precisely drive the mixer for the highest linearity and the lowest noise fgure. wideband filter most of the if fltering is done between the mixer and the if amplifer. this network is a 2nd order chebychev bandpass section, designed for 0.1db passband ripple. the 3db bandwidth is 220mhz, centered at 184mhz, see figure 3. additional lowpass fltering is done just before the adc. this flter serves to bandlimit the out of band noise entering the converter, as well as to isolate the output of the if amplifer from the sampling action of the converter. if frequency (mhz) 10 amplitude (dbfs) 210 310 16011060 260 360 9003 f03 410 0 ?20 ?40 ?10 ?5 ?30 ?25 ?15 ?35 ?45 ?50 figure 3. if filter response analog to digital converter as shown in figure 1, the analog-to-digital converter (adc) is a cmos pipelined multistep converter. the converter has fve pipelined adc stages; a sampled analog input will result in a digitized value fve cycles later (see the tim- ing diagram section). the encode input is differential for improved common mode noise immunity. the adc has two phases of operation, determined by the state of the differential enc + /enc C input pins. for brevity, the text will refer to enc + greater than enc C as enc high and enc + less than enc C as enc low. each pipelined stage shown in figure 1 contains an adc, a reconstruction dac and an interstage residue amplifer. in operation, the adc quantizes the input to the stage and the quantized value is subtracted from the input by the dac to produce a residue. the residue is amplifed and output by the residue amplifer. successive stages operate out of phase so that when the odd stages are outputting their residue, the even stages are acquiring that residue and visa versa. when enc is low, the analog input is sampled differentially directly onto the input sample-and-hold capacitors, inside the input s/h shown in the block diagram. at the instant that enc transitions from low to high, the sampled input is held. while enc is high, the held input voltage is buffered by the s/h amplifer which drives the frst pipelined adc stage. the frst stage acquires the output of the s/h dur- ing this high phase of enc. when enc goes back low, the frst stage produces its residue which is acquired by the second stage. at the same time, the input s/h goes back to acquiring the analog input. when enc goes back high, the second stage produces its residue which is acquired by the third stage. an identical process is repeated for the third and fourth stages, resulting in a fourth stage residue that is sent to the ffth stage adc for fnal evaluation. each adc stage following the frst has additional range to accommodate fash and amplifer offset errors. results from all of the adc stages are digitally synchronized such that the results can be properly combined in the correction logic before being sent to the output buffer. o pera t ion
ltm9003 9003f a pplica t ions i n f or m a t ion rf input port the mixers rf input is shown in figure 4 and is internally matched from 1.1ghz to 1.8ghz, requiring no external components over this frequency range. the input return loss, shown in figure 5, is typically 12db at the band edges. the input match at the lower band edge can be optimized with a shunt 3.3pf capacitor at pin g1, which improves the 0.8ghz return loss to greater than 25db. likewise, the 2ghz match can be improved to greater than 25db with a series 3.9nh inductor and a 1pf shunt capacitor. measured rf input return losses for these three cases are plotted in figure 5. figure 4. rf input schematic rf in z o = 50 l = l (mm) c5 rf 9003 f04 rf in c5 l5 low-pass match for 450mhz, 900mhz and 3.6ghz rf high-pass match for 2.6ghz rf and wideband rf to mixer ltm9003 figure 5. rf input return loss with and without matching frequency (mhz) 100 ?30 rf port return loss (db) ?25 ?20 ?15 ?10 1000 10000 9003 f05 ?5 0 800mhz match (3.3pf) 2ghz match (3.9nh + 1pf) no matching elements this series transmission line/shunt capacitor matching topology allows the ltm9003 to be used for multiple frequency standards without circuit board layout modifca- tions. the series transmission line can also be replaced with a series chip inductor for a more compact layout. rf input impedance and s11 versus frequency (with no external matching) are listed in table 1 and referenced to pin g1. the s11 data can be used with a microwave circuit simulator to design custom matching networks and simulate board-level interfacing to the rf input flter. table 1a. rf input impedance vs frequency (ltm9003-aa) frequency (mhz) input impedance s11 mag angle 500 20.3 + j7 0.57 143 600 23.6 + j6.7 0.53 137.9 700 27.1 + j6.1 0.48 132.7 800 30.8 + j5.3 0.43 127 900 34.9 + j4.2 0.38 120.4 1000 39.4 + j2.9 0.33 112.6 1100 44.6 + j1.4 0.28 102.8 1200 50.1 0.22 89.8 1300 56 C j1 0.17 70.4 1400 61.5 C j1.2 0.14 42.2 1500 66 C j0.3 0.14 6.6 1600 68.7 + j1.4 0.17 C21.5 1700 69 + j3.2 0.22 C41 1800 67.5 + j4.5 0.27 C54 1900 64.3 + j4.7 0.32 C64.3 2000 60.8 + j4.1 0.36 C72.2 2100 56.7 + j2.8 0.4 C79.5 2200 52.7 + j1.2 0.43 C85.8 2300 48.6 C j0.6 0.46 C92.1 2400 44.7 C j2.3 0.48 C98 2500 40.8 C j4 0.5 C104.3 2600 37 C j5.3 0.51 C110.5 2700 33.1 C j6.3 0.52 C117.2 2800 29.4 C j6.9 0.53 C124.3 2900 26 C j7 0.53 C131.7 3000 22.9 C j6.7 0.53 C139.6
ltm9003 9003f table 1b. rf input impedance vs frequency (ltm9003-ab) frequency (mhz) input impedance s11 mag angle 500 19.8 + j7.3 0.59 143 600 22.7 + j7 0.55 138.4 700 25.7 + j6.6 0.51 133.9 800 28.8 + j5.9 0.47 129.2 900 32.3 + j5.1 0.42 123.9 1000 36.1 + j3.9 0.38 117.9 1100 40.5 + j2.6 0.32 110.6 1200 45.4 + j1.1 0.26 101.3 1300 50.8 C j0.2 0.2 87.6 1400 56.3 C j0.9 0.15 65.6 1500 61.4 C j0.7 0.12 27.5 1600 65.3 + j0.5 0.14 C13.1 1700 67.4 + j2.4 0.19 C37.9 1800 67.3 + j4.1 0.25 C52.4 1900 65.7 + j5.1 0.31 C61.9 2000 63.2 + j5.2 0.37 C68.9 2100 60.4 + j4.7 0.42 C74.4 2200 57.6 + j3.7 0.46 C79.1 2300 55 + j2.6 0.49 C83 2400 52.4 + j1.3 0.51 C86.7 2500 49.9 0.53 C90.1 2600 47.4 C j1.4 0.54 C93.7 2700 44.8 C j2.7 0.55 C97.3 2800 41.9 C j3.9 0.55 C101.6 2900 39 C j5 0.55 C106.3 3000 35.7 C j5.9 0.54 C111.9 lo input port the mixers lo input, shown in figure 6, is internally matched from 0.9ghz to 3.5ghz. lo input matching near 600mhz requires the series inductor (l4)/shunt capaci- tor (c4) network shown in figure 6. likewise, the 2ghz match can be improved by using l4 = 2.7h, c4 = 0.5pf. measured lo input return losses for these three cases are plotted in figure 7. the optimum lo drive is C3dbm for lo frequencies above 1.2ghz, although the amplifers are designed to accommo- date several db of lo input power variation without signifcant mixer performance variation. below 1.2ghz, 0dbm lo drive is recommended for optimum noise fgure, although C3dbm will still deliver good conversion gain and linearity. a pplica t ions i n f or m a t ion figure 6. lo input schematic lo in c4 l4 lo v cc2 limiter v ref 9003 f06 ltm9003 external matching for lo < 1ghz to mixer regulator custom matching networks can be designed using the port impedance data listed in table 2. this data is referenced to the lo pin with no external matching. table 2a. lo input impedance vs frequency (ltm9003-aa) frequency (mhz) input impedance s11 mag angle 500 10.3 C j6.1 0.73 C159.1 600 9.7 + j2.2 0.68 172.4 700 18.7 + j8.2 0.64 141.8 800 37 + j6.2 0.6 108.4 900 64.5 C j9.9 0.59 72.7 1000 109.7 C j42.2 0.6 38.3 1100 206.6 C j35.9 0.63 7.9 1200 183.8 + j70 0.66 C17.1 1300 115.4 + j59.4 0.68 C37.3 1400 86.7 + j35.2 0.7 C53.7 1500 70.7 + j18.5 0.71 C67.4 1600 59.3 + j7.4 0.7 C79.2 1700 50.2 + j0.2 0.7 C89.7 1800 42.6 C j4.5 0.68 C99.6 1900 35.9 C j7.2 0.66 C109.2 2000 30.2 C j8.3 0.63 C118.9 2100 25.6 C j8.1 0.59 C129.2 2200 22.4 C j6.7 0.54 C140.3 2300 20.8 C j4.6 0.48 C152.3 2400 21.5 C j2.1 0.42 C165.5 2500 24.2 0.35 C179.8 2600 28.9 + j1.3 0.28 163.9 2700 35.3 + j1.5 0.21 145.1 2800 42.6 + j0.9 0.16 121.1 2900 50.3 0.12 88.6 3000 57.7 C j0.6 0.1 45.8
ltm9003 9003f a pplica t ions i n f or m a t ion table 2b. lo input impedance vs frequency (ltm9003-ab) frequency (mhz) input impedance s11 mag angle 500 14.3 C j7.5 0.68 C150.6 600 12.6 C j2.4 0.61 C170.4 700 15.8 + j1.9 0.53 170.8 800 22.7 + j4.1 0.44 151.5 900 32.5 + j3.8 0.35 130.2 1000 44.2 + j1.3 0.25 104.9 1100 56.3 C j1.2 0.18 70.3 1200 66 C j1.3 0.15 26.4 1300 70.7 + j1 0.18 C12.8 1400 69.9 + j3.1 0.21 C37.8 1500 66 + j3.7 0.25 C54.1 1600 61.8 + j3.3 0.27 C65.5 1700 58.1 + j2.4 0.28 C73.4 1800 54.9 + j1.5 0.29 C79.8 1900 52.7 + j0.8 0.28 C84.2 2000 50.7 + j0.2 0.28 C88.5 2100 49.4 C j0.2 0.27 C91.4 2200 47.8 C j0.5 0.25 C95.5 2300 46.7 C j0.7 0.23 C98.9 2400 45.7 C j0.8 0.2 C103.3 2500 45.5 C j0.7 0.17 C106.8 2600 46.4 C j0.4 0.13 C107.1 2700 48.7 C j0.1 0.1 C97.9 2800 50.9 + j0.1 0.09 C84.2 2900 52.9 + j0.3 0.09 C72.5 3000 54.6 + j0.5 0.11 C66.7 mixer enable interface the voltage necessary to turn on the mixer is 2.7v. to dis- able the mixer, the enable voltage must be less than 0.3v. if the mix_en pin is allowed to foat, the mixer will tend to remain in its last operating state. thus it is not recom- mended that the enable function be used in this manner. if the shutdown function is not required, then the mix_en pin should be connected directly to v cc1 . amplifer enable interface the amp_en pin self-biases to v cc2 through a 30k resis- tor. the pin must be pulled below 0.8v in order to disable the amplifer. driving the adc clock input the noise performance of the adc can depend on the encode signal quality as much as on the analog input. the enc + /enc C inputs are intended to be driven differentially, primarily for noise immunity from common mode noise sources. each input is biased through a 4.8k resistor to a 1.5v bias. the bias resistors set the dc operating point for transformer coupled drive circuits and can set the logic threshold for single-ended drive circuits. any noise present on the encode signal will result in ad- ditional aperture jitter that will be rms summed with the inherent adc aperture jitter. in applications where jitter is critical (high input frequen- cies) take the following into consideration: 1. differential drive should be used. 2. use as large an amplitude as possible; if transformer coupled use a higher turns ratio to increase the amplitude. 3. if the adc is clocked with a sinusoidal signal, flter the encode signal to reduce wideband noise. 4. balance the capacitance and series resistance at both encode inputs so that any coupled noise will appear at both inputs as common mode noise. the encode inputs have a common mode range of 1.2v to 2.0v. each input may be driven from ground to v dd for single-ended drive. figure 7. lo input return loss with and without matching frequency (mhz) 100 ?30 return loss (db) ?25 ?20 ?15 ?10 1000 10000 9003 f07 ?5 0 600mhz match (6.8nh + 5.6pf) 2ghz match (2.7nh + 0.5pf) no matching elements
ltm9003 9003f v dd v dd ltm9003 9003 f08 v dd enc ? enc + 1.5v bias 1.5v bias 0.1f t1 ma/com etc1-1-13 clock input 100 8.2pf 0.1f ?? 4.8k 4.8k to internal adc circuits a pplica t ions i n f or m a t ion maximum and minimum conversion rates the maximum conversion rate for the adc is 250msps. for the adc to operate properly, the encode signal should have a 50% (5%) duty cycle. each half cycle must have at least 1.9ns for the adc internal circuitry to have enough settling time for proper operation. achieving a precise 50% duty cycle is easy with differential sinusoidal drive using a transformer or using symmetric differential logic such as pecl or lvds. the lower limit of the sample rate is determined by the droop of the sample-and-hold circuits. the pipelined ar- chitecture of this adc relies on storing analog signals on small valued capacitors. junction leakage will discharge the capacitors. the specifed minimum operating frequency for the ltm9003 is 1msps. clock duty cycle stabilizer an optional clock duty cycle stabilizer circuit can be used if the input clock has a non 50% duty cycle. this circuit uses the rising edge of the enc + pin to sample the analog input. the falling edge of enc + is ignored and the internal falling edge is generated by a phase-locked loop. the input clock duty cycle can vary from 40% to 60% and the clock duty cycle stabilizer will maintain a constant 50% internal duty cycle. if the clock is turned off for a long period of time, the duty cycle stabilizer circuit will require one hundred clock cycles for the pll to lock onto the input clock. to use the clock duty cycle stabilizer, the mode pin should be connected to 1/3v dd or 2/3v dd using external resistors. clock sources for undersampling undersampling is especially demanding on the clock source and the higher the input frequency, the greater the sensitivity to clock jitter or phase noise. a clock source that degrades snr of a full-scale signal by 1db at 70mhz will degrade snr by 3db at 140mhz, and 4.5db at 190mhz. in cases where absolute clock frequency accuracy is relatively unimportant and only a single adc is required, a canned oscillator from vendors such as saronix or vectron can be placed close to the adc and simply connected directly to the adc. if there is any distance to the adc, some source termination to reduce ringing that may occur even over a fraction of an inch is advisable. you must not allow the clock to overshoot the supplies or performance will suffer. do not flter the clock signal with a narrow band flter unless you have a sinusoidal clock source, as the rise and fall time artifacts present in typical digital clock signals will be translated into phase noise. figure 8. transformer driven enc + /enc C figure 9. single-ended enc driver, not recommended for low jitter figure 10. enc drive using lvds 9003 f09 enc ? 1.5v v threshold = 1.5v enc + 0.1f ltm9003 9003 f10 enc ? enc + lvds clock 0.1f ltm9003 0.1f
ltm9003 9003f a pplica t ions i n f or m a t ion the lowest phase noise oscillators have single-ended sinusoidal outputs, and for these devices the use of a flter close to the adc may be benefcial. this flter should be close to the adc to both reduce roundtrip refection times, as well as reduce the susceptibility of the traces between the flter and the adc. if the circuit is sensitive to close- in phase noise, the power supply for oscillators and any buffers must be very stable, or propagation delay variation with supply will translate into phase noise. even though these clock sources may be regarded as digital devices, do not operate them on a digital supply. if your clock is also used to drive digital devices such as an fpga, you should locate the oscillator, and any clock fan-out devices close to the adc, and give the routing to the adc precedence. the clock signals to the fpga should have series termination at the driver to prevent high frequency noise from the fpga disturbing the substrate of the clock fan-out device. if you use an fpga as a programmable divider, you must re-time the signal using the original oscillator, and the re-timing fip-fop as well as the oscillator should be close to the adc, and powered with a very quiet supply. for cases where there are multiple adcs, or where the clock source originates some distance away, differential clock distribution is advisable. this is advisable both from the perspective of emi, but also to avoid receiving noise from digital sources both radiated, as well as propagated in the waveguides that exist between the layers of multilayer pcbs. the differential pairs must be close together and distanced from other signals. the differential pair should be guarded on both sides with copper distanced at least 3x the distance between the traces, and grounded with vias no more than 1/4 inch apart. digital outputs table 3 shows the relationship between the analog input voltage, the digital data bits, and the overfow bit. table 3. output codes vs input voltage input (sense = v dd ) of d11 C d0 (offset binary) d11 C d0 (2s complement) overvoltage 1 1111 1111 1111 0111 1111 1111 maximum 0 0 1111 1111 1111 1111 1111 1110 0111 1111 1111 0111 1111 1110 0.000000v 0 0 0 0 1000 0000 0001 1000 0000 0000 0111 1111 1111 0111 1111 1110 0000 0000 0001 0000 0000 0000 1111 1111 1111 1111 1111 1110 minimum 0 0 0000 0000 0001 0000 0000 0000 1000 0000 0001 1000 0000 0000 undervoltage 1 0000 0000 0000 1000 0000 0000 digital output buffers figure 11 shows an equivalent circuit for a differential output pair in the lvds output mode. a 3.5ma current is steered from out+ to outC or vice versa which creates a 350mv differential voltage across the 100 termination resistor at the lvds receiver. a feedback loop regulates the common mode output voltage to 1.25v. for proper operation each lvds output pair needs an external 100 figure 11. digital output in lvds mode ltm9003 9003 f11 ov dd lvds receiver ognd 1.25v d d d d out + 0.1f 2.5v out ? 100 + ? 3.5ma 10k 10k
ltm9003 0 9003f termination resistor, even if the signal is not used (such as of + /of C or clkout + /clkout C ). to minimize noise the pc board traces for each lvds output pair should be routed close together. to minimize clock skew all lvds pc board traces should have about the same length. data format the ltm9003 parallel digital output can be selected for offset binary or 2s complement format. the format is selected with the mode pin. connecting mode to gnd or 1/3v dd selects offset binary output format. connecting mode to 2/3v dd or v dd selects 2s complement output format. an external resistor divider can be used to set the 1/3v dd or 2/3v dd logic values. table 4 shows the logic states for the mode pin. table 4. mode pin function mode pin output format clock duty cycle stabilizer 0 straight binary off 1/3v dd straight binary on 2/3v dd 2s complement on v dd 2s complement off overfow bit an overfow output bit indicates when the converter is overranged or underranged. a differential logic high on the of + /of C pins indicates an overfow or underfow. output clock the ltm9003 has a delayed version of the enc + input avail- able as a digital output, clkout. the clkout pin can be used to synchronize the converter data to the digital system. this is necessary when using a sinusoidal encode. data will be updated just after clkout + /clkout C rises and can be latched on the falling edge of clkout + /clkout C . output driver power ov dd should be connected to a 2.5v supply and ognd should be connected to gnd. output enable the outputs may be disabled with the output enable pin, oe . in lvds output mode oe high disables all data outputs including of and clkout. the data access and bus relinquish times are too slow to allow the outputs to be enabled and disabled during full speed operation. the output hi-z state is intended for use during long periods of inactivity. the hi-z state is not a truly open circuit; the output pins that make an lvds output pair have a 20k resistance between them. sleep and nap modes the converter may be placed in shutdown or nap modes to conserve power. connecting shdn to gnd results in normal operation. connecting shdn to v dd and oe to v dd results in sleep mode, which powers down all circuitry including the reference and the adc typically dissipates 1.5mw. when exiting sleep mode, it will take milliseconds for the output data to become valid because the reference capacitors have to recharge and stabilize. connecting shdn to v dd and oe to gnd results in nap mode and the adc typically dissipates 30mw. in nap mode, the on-chip reference circuit is kept on, so that recovery from nap mode is faster than that from sleep mode, typically taking 100 clock cycles. in both sleep and nap modes, all digital outputs are disabled and enter the hi-z state. supply sequencing the v cc1 and v cc2 pins provide the supply to the mixer and amplifer, respectively, and the v dd pin provides the supply to the adc. the mixer, amplifer and adc are sepa- rate integrated circuits within the ltm9003. separate linear regulators can be used without additional supply sequenc- ing circuitry if they have common input supplies. a pplica t ions i n f or m a t ion
ltm9003 9003f grounding and bypassing the ltm9003 requires a printed circuit board with a clean unbroken ground plane; a multilayer board with an internal ground plane is recommended. the pinout of the ltm9003 has been optimized for a fow-through layout so that the interaction between inputs and digital outputs is minimized. ample ground pads facilitate a layout that ensures that digital and analog signal lines are separated as much as possible. the ltm9003 is internally bypassed with the adc (v dd ), amplifer (v cc2 ) and mixer (v cc1 ) supplies returning to a common ground (gnd). the digital output supply (ov dd ) is returned to ognd. additional bypass capacitance is optional and may be required if power supply noise is signifcant. heat transfer most of the heat generated by the ltm9003 is transferred through the bottom-side ground pads. for good electrical and thermal performance, it is critical that all ground pins are connected to a ground plane of suffcient area with as many vias as possible. recommended layout the high integration of the ltm9003 makes the pcb board layout very simple and easy. however, to optimize its electri- cal and thermal performance, some layout considerations are still necessary. ? use large pcb copper areas for ground. this helps to dissipate heat in the package through the board and also helps to shield sensitive on-board analog signals. common ground (gnd) and output ground (ognd) are electrically isolated on the ltm9003, but can be connected on the pcb underneath the part to provide a common return path. ? use multiple ground vias. using as many vias as pos- sible helps to improve the thermal performance of the board and creates necessary barriers separating analog and digital traces on the board at high frequencies. ? separate analog and digital traces as much as possible, using vias to create high-frequency barriers. this will re- duce digital feedback that can reduce the signal-to-noise ratio (snr) and dynamic range of the ltm9003. figures 12 through 15 give a good example of the recom- mended layout. the quality of the paste print is an important factor in producing high yield assemblies. it is recommended to use a type 3 or 4 printing no-clean solder paste. the solder stencil design should follow the guidelines outlined in application note 100. the ltm9003 employs gold-fnished pads for use with pb-based or tin-based solder paste. it is inherently pb-free and complies with the jedec (e4) standard. the materi- als declaration is available online at http://www.linear. com/leadfree/mat_dec.jsp. a pplica t ions i n f or m a t ion
ltm9003 9003f figure 12. layer 1 component side figure 13. layer 2 figure 14. layer 3 figure 15. backside a pplica t ions i n f or m a t ion
ltm9003 9003f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. p ackage descrip t ion notes: 1. dimensioning and tolerancing per asme y14.5m-1994 2. all dimensions are in millimeters land designation per jesd mo-222, spp-010 5. primary datum -z- is seating plane 6. the total number of pads: 108 4 3 details of pad #1 identifier are optional, but must be located within the zone indicated. the pad #1 identifier may be either a mold or marked feature symbol aaa bbb eee tolerance 0.15 0.10 0.05 2.22 ? 2.42 detail b detail b substrate mold cap 0.27 ? 0.37 1.95 ? 2.05 z 11.25 bsc package top view 15 bsc 4 pad 1 corner x y aaa z aaa z detail a 10.16 bsc 1.27 bsc 13.97 bsc 11 10 9 8 7 6 5 4 3 2 package bottom view dia (0.635) pad 1 3 pads see notes 12 1 a b c d e f g h j suggested pcb layout top view 1.270 1.270 0.000 2.540 2.540 3.810 3.810 5.080 5.080 6.985 6.985 5.715 5.715 4.445 4.445 3.175 3.175 1.905 1.905 0.635 0.635 0.000 lga 108 0707 rev ? package in tray loading orientation ltmxxxxxx module tray pin 1 bevel component pin ?a1? // bbb z 0.22 45 chamfer detail a 0.630 0.025 sq. 108x s yxeee lga package 108-lead (15mm s 11.25mm s 2.32mm) (reference ltc dwg # 05-08-1757 rev ?)
ltm9003 9003f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com ? linear technology corporation 2010 lt 0910 ? printed in usa r ela t e d p ar t s part number description comments ltc2240-10 10-bit, 170msps, 2.5v adc, lvds outputs 445mw, 60.6db snr, 78db sfdr, 64-pin qfn ltc2240-12 12-bit, 170msps, 2.5v adc, lvds outputs 445mw, 65.5db snr, 80db sfdr, 64-pin qfn ltc2241-10 10-bit, 210msps, 2.5v adc, lvds outputs 585mw, 60.6db snr, 78db sfdr, 64-pin qfn ltc2241-12 12-bit, 210msps, 2.5v adc, lvds outputs 585mw, 65.5db snr, 78db sfdr, 64-pin qfn ltc2242-10 10-bit, 250msps, 2.5v adc, lvds outputs 740mw, 60.5db snr, 78db sfdr, 64-pin qfn ltc2242-12 12-bit, 250msps, 2.5v adc, lvds outputs 740mw, 65.4db snr, 78db sfdr, 64-pin qfn ltc6410 differential if amplifer with confgurable input impedance 1.4ghz, C3db bw, 6db fixed voltage gain (50 system), 36dbm oip3 lt5527 400mhz to 3.7ghz, 5v high signal level downconverting mixer 23.5dbm iip3 at 1.9ghz, nf = 12.5db, single-ended rf and lo ports lt5557 400mhz to 3.8ghz, 3.3v high signal level downconverting mixer 24.7dbm iip3 at 1.9ghz, nf = 11.7db, single-ended rf and lo ports, 3.3v supply ltm9001-aa 16-bit, if/baseband receiver subsystem 16-bit, 130msps adc, 20db gain amplifer, anti-alias filter, internal bypass capacitance ltm9002-aa dual 14-bit, if/baseband receiver subsystem dual 14-bit, 125msps adc, dual 26db gain amplifers, anti-alias filters, auxiliary dac for gain adjustment, internal bypass capacitance

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